With the continuous development of integrated circuits toward ultra-large-scale integrated circuits, the circuit density of the integrated circuit keeps increasing, and more and more unit components are included, accompanied by a reduction of the unit component size. When the size of the MOS device decreases, the channel of the MOS device is also shortened. Since the channel is shortened, the shallow channel approximation of the MOS device is broken. As a result, various types of adverse physical effects (especially the short channel effect) begin to occur, which degrades the device performance and reliability and limits a further decrease of the device size.
To further reduce the size of MOS devices, a multi-faceted field-effect transistor structure has been developed to improve the controllability of the gate of MOS devices and to suppress the short channel effect. As a typical example, the popular fin-type field-effect transistor (FinFET) is a multi-faceted gate structure transistor.
The FinFET is a three-dimensional structure including a substrate and a plurality of discrete fins on the substrate, and isolating portions are located between the fins. The gate crosses over the fins and covers the top and sidewall surfaces of the fins. As this three-dimensional structure is very different from traditional planar transistor structure, the electrical performance of devices can be significantly influenced by even a portion of improper technical process.
The source, drain, and channel of the FinFET are all located within the fins, and the formation process of the fins can directly affect the performance of the formed transistor. However, conventionally formed semiconductor structures with fins usually have poor electrical performance and needs to be improved.